The present invention relates to a semiconductor device and a manufacturing method thereof. The present invention is applicable to, for example, manufacturing of a semiconductor device having a nonvolatile memory and a capacitor element.
As an electrically writable/erasable nonvolatile semiconductor storage device, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has been widely used. Such a storage device has a conductive floating gate electrode surrounded by an oxide film, or a trapping insulation film under the gate electrode of a MISFET. The storage device uses the charge accumulation state at the floating gate or the trapping insulation film as stored information, and read out the information as a threshold value of the transistor.
The trapping insulation film denotes an insulation film capable of accumulating electric charges. As one example thereof, mention may be made of a silicon nitride film. Implantation/discharge of electric charges into such a charge accumulation region causes each MISFET to be shifted in threshold value and to operate as a storage element. The nonvolatile storage devices using a trapping insulation film include a split gate type cell using a MONOS (Metal Oxide Nitride Oxide Semiconductor) film.
Whereas, as the formation method of a gate electrode, a so-called gate-last process is known in which after forming a dummy gate electrode over a substrate, the dummy gate electrode is replaced with a metal gate electrode, or the like. When the gate-last process is used, it is difficult to form a capacitor element in which the lower electrode is formed at the same height as that of the gate electrode, and the upper electrode is formed over the lower electrode.
In contrast, a capacitor element in which the semiconductor substrate is used as the lower electrode, and the upper electrode is formed at the same height as that of the gate electrode can be merged with a storage element, and the like formed using the gate-last process over the semiconductor substrate. In such a capacitor element, the upper electrode is partially embedded in the trenches formed in the main surface of the semiconductor substrate, so that the facing area of the upper electrode and the semiconductor substrate can be increased. This can increase the capacitance.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2001-85633) describes a capacitor element in which a capacitance is generated between a substrate and a first gate over the substrate, and further, a capacitance is generated between the first gate and a second gate over the first gate.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2003-309182) describes as follows: in a capacitor element for generating a capacitance between a substrate and an electrode over the substrate, the electrode is partially embedded in trenches in the top surface of the substrate.
Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2014-154790) describes that a memory cell is formed using the gate-last process.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2001-85633
[Patent Document 2] Japanese Unexamined Patent Application Publication No. 2003-309182
[Patent Document 3] Japanese Unexamined Patent Application Publication No. 2014-154790